Beispiel des EEPROM-Decoders
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PC DIMM Serial Presence Detect Tester/Decoder
Written by Philip Edelbrock. Copyright 1998, 1999.
Modified by Christian Zuckschwerdt
Version 0.6
| Decoding EEPROM | /proc/sys/dev/sensors/eeprom-i2c-0-50 |
| Guessing DIMM is in | bank 1 |
| The Following is Required Data and is Applicable to all DIMM Types | |
| # of bytes written to SDRAM EEPROM | 128 |
| Total number of bytes in EEPROM | 256 |
| Fundemental Memory type | SDRAM |
| Number of Row Address Bits (SDRAM only) | 12 |
| Number of Col Address Bits (SDRAM only) | 9 |
| Number of Module Rows | 2 |
| Data Width (SDRAM only) | 64 |
| Module Interface Signal Levels | LVTTL |
| Cycle Time (SDRAM) highest CAS latency | 8ns |
| Access Time (SDRAM) | 6ns |
| Module Configuration Type | No Parity |
| Refresh Type | Self Refreshing |
| Refresh Rate | Normal (15.625uS) |
| Primary SDRAM Component Bank Config | No Bank2 OR Bank2 = Bank1 width |
| Primary SDRAM Component Widths | 8 |
| Error Checking SDRAM Component Bank Config | No Bank2 OR Bank2 = Bank1 width |
| Error Checking SDRAM Component Widths | Undefined! |
| Min Clock Delay for Back to Back Random Access | 1 |
| The Following Apply to SDRAM DIMMs ONLY | |
| Burst lengths supported | Burst Length = 1 Burst Length = 2 Burst Length = 4 Burst Length = 8 Burst Length = Page |
| Number of Device Banks | 4 |
| Supported CAS Latencies | CAS Latency = 2 CAS Latency = 3 |
| Supported CS Latencies | CS Latency = 0 |
| Supported WE Latencies | WE Latency = 0 |
| SDRAM Module Attributes | (None Reported) |
| SDRAM Device Attributes (General) | Supports Auto-Precharge Supports Precharge All Supports Write1/Read Burst Lower VCC Tolerance:10% Upper VCC Tolerance:10% |
| SDRAM Cycle Time (2nd highest CAS) | 10nS |
| SDRAM Access from Clock Time (2nd highest CAS) | 6nS |
| The Following are Optional (may be Bogus) | |
| SDRAM Cycle Time (3rd highest CAS) | Undefined! |
| SDRAM Access from Clock Time (3rd highest CAS) | Undefined! |
| The Following are Required (for SDRAMs) | |
| Minumum Row Precharge Time | 20nS |
| Row Active to Row Active Min | 20nS |
| RAS to CAS Delay | 20nS |
| Min RAS Pulse Width | 50nS |
| The Following are Required and Apply to ALL DIMMs | |
| Row Densities | 64 MByte |
| The Following are Proposed and Apply to SDRAM DIMMs | |
| Command and Address Signal Setup Time | 2nS |
| Command and Address Signal Hold Time | 1nS |
| Data Signal Setup Time | 2nS |
| Data Signal Hold Time | 1nS |
| SPD Revision code | 12 |
| EEPROM Checksum of bytes 0-62 | 0xE6 (verses calculated: 0xE6) |
| Manufacturer's JEDEC ID Code | 0x0000000000000000 |
| Manufacturer's JEDEC ID Code | ("^@^@^@^@^@^@^@^@") |
| Manufacturing Location Code | 0x00 |
| Manufacurer's Part Number:" | ^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@ |
| Revision Code | 0x0000 |
| Manufacturing Date | 0x0000 |
| Intel Specification for Frequency | 100MHz |
| Intel Spec Details for 100MHz Support | Intel Concurrent AutoPrecharge CAS Latency = 2 CAS Latency = 3 Junction Temp B (100 degrees C) CLK 3 Connected CLK 2 Connected CLK 1 Connected CLK 0 Connected Double Sided DIMM |
| Decoding EEPROM | /proc/sys/dev/sensors/eeprom-i2c-0-51 |
| Guessing DIMM is in | bank 2 |
| The Following is Required Data and is Applicable to all DIMM Types | |
| # of bytes written to SDRAM EEPROM | 128 |
| Total number of bytes in EEPROM | 256 |
| Fundemental Memory type | SDRAM |
| Number of Row Address Bits (SDRAM only) | 12 |
| Number of Col Address Bits (SDRAM only) | 9 |
| Number of Module Rows | 2 |
| Data Width (SDRAM only) | 64 |
| Module Interface Signal Levels | LVTTL |
| Cycle Time (SDRAM) highest CAS latency | 10ns |
| Access Time (SDRAM) | 6ns |
| Module Configuration Type | No Parity |
| Refresh Type | Self Refreshing |
| Refresh Rate | Normal (15.625uS) |
| Primary SDRAM Component Bank Config | No Bank2 OR Bank2 = Bank1 width |
| Primary SDRAM Component Widths | 8 |
| Error Checking SDRAM Component Bank Config | No Bank2 OR Bank2 = Bank1 width |
| Error Checking SDRAM Component Widths | Undefined! |
| Min Clock Delay for Back to Back Random Access | 1 |
| The Following Apply to SDRAM DIMMs ONLY | |
| Burst lengths supported | Burst Length = 1 Burst Length = 2 Burst Length = 4 Burst Length = 8 Burst Length = Page |
| Number of Device Banks | 4 |
| Supported CAS Latencies | CAS Latency = 1 CAS Latency = 2 CAS Latency = 3 |
| Supported CS Latencies | CS Latency = 0 |
| Supported WE Latencies | WE Latency = 0 |
| SDRAM Module Attributes | (None Reported) |
| SDRAM Device Attributes (General) | Supports Early RAS# Recharge Supports Auto-Precharge Supports Precharge All Supports Write1/Read Burst Lower VCC Tolerance:10% Upper VCC Tolerance:10% |
| SDRAM Cycle Time (2nd highest CAS) | 15nS |
| SDRAM Access from Clock Time (2nd highest CAS) | 7nS |
| The Following are Optional (may be Bogus) | |
| SDRAM Cycle Time (3rd highest CAS) | Undefined! |
| SDRAM Access from Clock Time (3rd highest CAS) | Undefined! |
| The Following are Required (for SDRAMs) | |
| Minumum Row Precharge Time | 20nS |
| Row Active to Row Active Min | 20nS |
| RAS to CAS Delay | 20nS |
| Min RAS Pulse Width | 50nS |
| The Following are Required and Apply to ALL DIMMs | |
| Row Densities | 64 MByte |
| The Following are Proposed and Apply to SDRAM DIMMs | |
| Command and Address Signal Setup Time | 2nS |
| Command and Address Signal Hold Time | 1nS |
| Data Signal Setup Time | 2nS |
| Data Signal Hold Time | 1nS |
| SPD Revision code | 1 |
| EEPROM Checksum of bytes 0-62 | 0x57 (verses calculated: 0x57) |
| Manufacturer's JEDEC ID Code | 0x0000000000000000 |
| Manufacturer's JEDEC ID Code | ("^@^@^@^@^@^@^@^@") |
| Manufacturing Location Code | 0x00 |
| Manufacurer's Part Number:" | ^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@ |
| Revision Code | 0x0000 |
| Manufacturing Date | 0x0000 |
| Intel Specification for Frequency | Undefined! |
| Intel Spec Details for 100MHz Support | Intel Concurrent AutoPrecharge CAS Latency = 2 CAS Latency = 3 Junction Temp A (90 degrees C) CLK 3 Connected CLK 2 Connected CLK 1 Connected CLK 0 Connected Double Sided DIMM |
| Number of SDRAM DIMMs detected and decoded | 2 |
